Welcome to Self-balancing Robot Car repository

13.Window Watchdog (WWDG)

Window Watchdog (WWDG)

Window Watchdog (WWDG)Hardware connectionControl principleSoftware ConfigurationSoftware CodeControl FunctionExperimental phenomenon

The tutorial combines LED, buzzer, and KEY to demonstrate the hardware fault detection function of the window watchdog (WWDG).

Hardware connection

Peripherals	Development board	Description
LED	PB3	The anode of the LED is connected to the development board PB3, and the cathode is connected to the development board GND
KEY1	PA8	One end of the KEY is connected to the PA8 pin, and the other end is connected to GND
Buzzer (active buzzer)	PA11

Control principle

The STM32F103RCT6 has two built-in watchdogs (independent watchdog and window watchdog), which are mainly used for system fault detection and recovery.

Watchdog	Function
Independent Watchdog	Used to detect whether the system is running normally
Window Watchdog	Used to detect system failures

Window Watchdog

The window watchdog (WWDG) is driven by the clock obtained by dividing the APB1 clock. It detects abnormal late or early operations of the application by configuring the time window.

Window Watchdog	Status
Feed the watchdog when the count value > window upper limit	Reset
Feed the watchdog when the window upper limit > count value > window lower limit	Do not reset
Count value < window lower limit	Reset


The main function of the window watchdog is to monitor the working status of the system and prevent deadlock or infinite loop caused by software errors or unexpected events

Independent watchdog feature
Free-running down counter
Conditional reset
A reset is generated when the down counter is reloaded outside the window
A reset is generated when the down counter value is less than 0x40
If the watchdog is enabled and interrupts are enabled
When the down counter is equal to 0x40, an early wake-up interrupt (EWI) is generated to reload the counter to avoid WWDG reset

Window watchdog timeout: PCLK1=36MHz

WDGB	Minimum timeout	Maximum timeout
0	113us	7.28ms
1	227us	14.56ms


xxxxxxxxxx
The frequency division number set in the tutorial is 8, the window value is 43, and the count value is 54

T_{W W D G (m s)} = T_{P C L K 1} * 4096 * 2^{W D G T B} * (T [5 : 0] + 1)

$T_{W W D G}$ : WWDG timeout time

$T_{P C L K 1}$ : APB1 time interval in ms

Example: Counter minus 1 time (PCLK1=36MHz, frequency division number is 8)

T_{W W D G (m s)} = T_{P C L K 1} * 4096 * 2^{W D G T B} * (T [5 : 0] + 1) = \frac{1}{36000} * 4096 * 2^{3} * (1) = 0.910 m s

Software Configuration

Software Code

Configure the Window Watchdog (WWDG) hardware fault detection function, no need to configure specific pins.


 Independent Watchdog (IWDG)
DMA-USART